Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing

Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing

Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing

Optimize key deep learning models on AMD GPUs Develop and finetune inference and serving engines for large language models Collaborate with AMD's architecture specialists to improve future products Collaborate with operator libraries team to analyze and optimize training and inference for deep learning Work in a distributed computing setting to optimize for both scale up

Analyze power consumption of new and existing micro architectural features of Next Generation High Performance CPU Cores. Analyze power characteristics of the latest Server/Client CPU workloads and use the data to influence microarchitecture decisions. Collaborate with the RTL team to improve the implementation. Asist them in interpreting power analysis results from tools

Develop and run tools, infrastructure, processes and flows to enable functional verification in the emulation environment Develop emulation testbench components to stimulate and monitor the Device Under Test Maintain and improve emulation infrastructure and methodology. Develop and execute on verification test plans in emulation environments Develop, simulate and debug di

Build system level channel simulations to ensure packages and PCBs are designed well and meet required SI/PI specifications. Review layouts to determine any areas that require additional refinement. Extract models for package, PCB and Sockets from vendors, collecting standardized models if available, and running through simulation. Run channel simulations to generate perf

Establish IP architecture project plans, milestones, and deliverables Utilize already established architecture development processes, and tangibly contributes to process improvements for higher efficiency. Creates JIRA projects & dashboards, and tracks feature development. Establish requirement to feature traceability via Jama and Jira Identifies, tracks, and mitigates pr

Complete complex mask design of analog, digital, and mixed signal circuits. Own major blocks of the custom IP designs. Direct/advise remote and local resources. Ensure all supplied data from resources are reviewed and meet milestone requirements. Schedule and forecast critical assigned blocks, maintaining schedule. Work closely with Engineering staff to ensure correct req

Manage inventory levels across multiple business units, ensuring optimal stock levels while minimizing excess inventory and carrying costs. Coordinate testing activities in laboratory environments, ensuring timely completion and accurate reporting of results. Allocate systems and resources according to the needs of various business units, balancing priorities and optimizi

Mentor and help with test and design debug, gather and update status and escalate issues to swim lane leads Tracking and updating master test plan and to detail issues in JIRA Work with Firmware, SOC Design and other Emulation engineers to debug and drive tests to completion Responsible for the design and development of test environment components to support the pre silic

Execute on RTL design and coding for various sections of the processor core pipeline and related logic. Collaborate with a team of hardware and software engineers to define the high level architecture. Participate in the definition of microarchitecture of next generation high performance processor cores. Contribute to design verification, synthesis, power reduction, timin

Conduct full review of existing HPC EDA infrastructure with grid, OS, and EDA tools teams as well as engineering technical leaders and re architect the future global hybrid on prem and multi cloud HPC infrastructure that is highly efficient, utilized, scalable, and cost effective. Propose innovative approaches and work collaboratively with peer teams to maximize grid perf

Drive workload and application level strategies internally and with industry partners / ecosystem. Partner with SoC design teams in providing a unified and clear platform / system level vision to influence AMDs SoC roadmap. Drive reference platform requirements and partner with engineering on balance of internal / external execution. Represent AMD datacenter system level

Be the primary point of contact for consolidating and disseminating competitive information related to AECG Adaptive SoC products, both internally and externally Develop and maintain compelling competitive collateral for AMD Adaptive SoC portfolio Provide the first line of response to sales and field teams by providing detailed competitive analysis that quantifies AMD Ada